Intellex Acquires Expert by Big Village

We're thrilled to announce that Intellex has acquired Expert by Big Village, effective March 22, 2024. This strategic move enhances our capabilities and strengthens our commitment to delivering exceptional solutions to our customers.

Stay tuned for more updates on how this acquisition will benefit our clients and experts.

For inquiries or more information, please contact us at info@intellex.com.

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Expert Details

CMOS/CCD Image Sensor, Analog Design, High-speed IC, and RF

ID: 732666 Ohio, USA

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Expert's specialties include researching, modeling and designing the readout and high-speed ADC for SPEAR communication system under ONR funded BAA at OSU in a commercial Bi-CMOS process.

Prior to joining the Ohio State University, Expert spent over 10 years in CMOS mixed-signal circuit design, praimarily in monolithic CMOS and ROIC imaging applications. From 2002 to 2003, he worked at Intel Corporation, Analog Design Center, in Chandler, AZ, evaluating and developing power management techniques for mobile applications.

In 2004, Expert joined present-day Aptina Imaging Corporation, where he worked for 3 years on the design and development of several CMOS image sensor products for the cellular phone market as a design engineer in the Mobile Image Sensor Group.

From 2007 to 2014, Expert worked at Forza Silicon Corporation, in Pasadena, CA, where he participated in various technical, business development and leadership roles to design and develop high-performance CMOS image sensors and ROICs for cinematography, medical, automotive, and defense camera system applications.

Expert has authored and co-authored 3 issued patents, 4 conference papers, and 2 pending patents.

Education

Year Degree Subject Institution
Year: 2014 Degree: PhD (in progress) Subject: High-Speed and RF IC Institution: The Ohio State University
Year: 2003 Degree: ME Subject: Electrical Engineering Institution: Northern Arizona University
Year: 2001 Degree: BSEE Subject: Electrical Engineering Institution: Northern Arizona University

Work History

Years Employer Title Department
Years: 2014 to 2016 Employer: The Ohio State University Title: Research Assistant Department: Electroscience Lab
Responsibilities:
His responsibilities include the design and development of STAR communication system high-speed ADC, ONR funded BAA.
Model and design of 2.667 GHz, 12-bit ADC in 8HP, 120 nm, Bi-CMOS process.
Years Employer Title Department
Years: 2007 to 2014 Employer: Forza Silicon Corp Title: Senior Design Engineer Department: Image sensor design
Responsibilities:
Expert was a key member of technical staff participating on various capacities in the architecture, design, and characterization of high-performance CMOS image sensors and ROICs for cinematography, medical, automotive, and defense camera system applications.
Years Employer Title Department
Years: 2004 to 2007 Employer: Micron Technology Title: Analog Design Engineer Department: Image sensor design
Responsibilities:
He conducted analog design projects for CMOS digital camera applications. Design blocks included schematic
and layout of VDAC, class AB buffers, row driver and decoder for pixel readout, boosters, and
ADC blocks. He wrote Ocean script to customize simulations post-processing, and assisting on
top-level chip integration and simulations.
Years Employer Title Department
Years: 2002 to 2003 Employer: Intel Corp Title: Intern Department: Analog Design Center
Responsibilities:
Expert handled power management chip development for switching voltage regulators and LDO including both system level (Verilog-A) and the transistor level design using Cadence ADE tools.

Government Experience

Years Agency Role Description
Years: 2010 to 2012 Agency: ONR/NSWCDD Role: Lead designer Description: SBIR contract
Years: 2012 to 2014 Agency: DARPA Role: FPA Lead dseigner SCENICC Description: BAA contract

Career Accomplishments

Associations / Societies
IEEE member
Licenses / Certifications
The 3-D Packaging Revolution Course, Threshold Systems, May 2012
Advanced CMOS Image Sensors Characterization Course: Albert J.P. Theuwissen 2012
Advanced CMOS Image Sensors Course: Albert J.P. Theuwissen 2010
CMOS Image Sensors Introduction Course: Albert J.P. Theuwissen 2008
Cadence Management Corp.: Project Management 05/13/05 & 11/02/2012
Mead Microelectronics: Low Voltage, Low Power Analog IC Design 03/27/06
Publications and Patents Summary
Expert has authored or co-authored 2 issued patents, 4 conference papers, and 3 pending patents.

Additional Experience

Marketing Experience
Business Development Lead: Provide design, test system development, and characterization labor & materials estimates, proposals, and SOWs. Raised over $2.4M in DoD funding opportunities for IR and visible light imaging applications through SBIR/BAA technical proposals and attending DoD technical workshops: SCENICC, DARPA BAA, Phase I and Phase II. Dual-Well FPA (See-Spot), NSWCDD, Navy SBIR, Phase I and Phase II.
Other Relevant Experience
His software experience includes:
Cadence & Mentor graphics (schematic editor, simulation environment, layout tools, LVS&DRC, and RC parasitic extraction), PSpice, hspice, nanosim, Matlab, Minitab, MathCad, LabView,
Flash, Visio

Languages: VHDL, Verilog-A, Verilog

Language Skills

Language Proficiency
English Able to use the language fluently and accurately on all levels pertinent to professional needs
Arabic Able to use the language fluently and accurately on all levels pertinent to professional needs

Fields of Expertise

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