Expert in Electronic Reliability & On-Chip ESD Protection
Expert has specified IC design requirements for electromigration. He has studied electromigration in aluminum interconnects of ICs. He has successfully failure analyzed CMOS exhibiting electromigration-induced open circuits caused by CMOS latch-up.
Having extensive experience in this area, Expert has calculated failure (hazard) rates for semiconductor devices and failure rate forecasts for CMOS ICs used in pacemakers. He has computed average and instantaneous failure rates and used Weibull and lognormal time-to-failure distributions. He has calculated the projected field failure rate in FITs (failures per billion device hours) for new IC designs based on gate oxide thickness; B-mode (extrinsic) gate oxide defect density, point-defect wafer yield; fault coverage; discovery distribution t50 and sigma; handling casualty rate, application temperature; die size; probe overvoltage stress time, voltage and duty cycle; burn-in type (static or dynamic), temperature, and post test efficiency for point and gross defects; IDDQ voltage and test limit; and time in application.
Expert has expertise in failure mechanisms such as silicon nodules, metallization step coverage, bonding wire, moisture, entrapped radioactive krypton (Kr85), PN junction leakage, tin whiskers, threshold voltage shift, time-dependent dielectric breakdown (TDDB), mild EOS or ESD damage in bipolar devices that can cause Hfe (beta) degradation, and flicker (1/f) noise in transistors and input offset voltage shift in operational amplifiers.
Expert is knowledgeable of threshold voltage, gm, SCR latch-up, instabilities, radiation effects, and drain-induced barrier lowering (DIBL). He has designed, tested, failure analyzed, and evaluated ICs.
Expert knows the effects of radioactive krypton (Kr85) on CMOS ICs. He also understands the physics of degradation due to gamma and neutron radiation.
Expert has extensive knowledge of the physics of limiting phenomena and safe operating area (SOA) of power transistors. He is familiar with common emitter current gain also known as beta and Hfe, Vceo, Vces, Vbeo, gm, early effect, base widening, emitter efficiency, base transport, minority carrier lifetime, thermal resistance, instabilities, temperature effects, radiation effects, gold doping, and failure mechanisms. He is knowledgeable of pnp and npn bipolar transistors, field effect transistors (FETs), uni-junction transistors, and thin film transistors (TFTs).
SILICON SEMICONDUCTOR DEVICE SECOND BREAKDOWN. For 15 years, Expert has worked with devices whose maximum current handling capability is limited by second breakdown. His experience in second breakdown encompasses Isb failures in power transistors to It2 failures in submicron CMOS nFET snapback devices.
Ever since the failure mechanism of aluminum metallization in integrated circuits emerged in the mid 1980s, Expert has worked with this potentially devastating problem. He can recognize stress voids by their characteristic slits; the voids can form during unbiased storage.
Expert presently works with various aspects of reliability including semiconductor devices and semiconductor memory. He has expertise in IC reliability screens for CMOS ICs. He is knowledgeable of forecasting failure rate and soft error rate (SER) as well as methods for accelerated testing for semiconductor memory. He is experienced in both static random access memory (SRAM) as well as nonvolatile memory such as EPROM, EEPROM, and FLASH. With 15 years experience in electron device reliability, he knows the physics and mathematics related to accelerated testing, infant mortality and long-term wearout, acceleration factors, Goldthwaite curves, and Arrhenius activation energy.
Expert has operated and designed SCRs. He is knowledgeable of methods of interpreting electrical overstress damage caused by exceeding limits such as dI/dt (time rate of change of current, I) and dV/dt (time rate of change of voltage, V), and by not providing adequate gate drive.
Expert's work involves predicting TDDB wearout rate of CMOS and BiMOS ICs. He is very familiar with E-model and 1/E-model for predicting the reliability of MOS devices due to TDDB.
Expert's 10 years experience in ESD includes failure analysis, safe handling, testing, training, and design of on-chip ESD protection structures. He knows how to use a radio receiver to detect ESD, how to use the photon (light) emission microscope for locating ESD damage, and how ordinary plastics induce destructive currents in semiconductor devices. In addition to the classic situations modeled by the human body model (HBM), the machine model (MM), the charged device model (CDM), and the field induced model (FIM), he is familiar with less common types of ESD events such as discharges between (1) plastic leadless chip carriers (PLCCs) sliding inside an "antistatic" shipping tube, (2) floating metal connectors and grounded devices in charged Teflon test fixtures, (3) Teflon boats of silicon wafers and metal table tops after rinse and Expert operations, and (4) silicon wafers and nearby metal resulting from application of charged plastic tape prior to the wafer saw operation.
Expert has extensive experience in resolving a variety of ESD problems in the workplace. He developed curriculum and taught an ESD course to more than 400 students. The four-hour course includes videotape, demonstrations using a Faraday cup, field meter, pith balls, nuclear ionizer radio receiver, and plastic materials including Teflon, Delrin, PVC, Kapton, and Tyvec. He has developed a measurement technique for quantifying the triboelectric generating properties of items such as latex gloves and finger cots, antistatic plastics, plastic films, and smocks.
Expert has expertise in EOS and ESD damage interpretation as well as specific semiconductor devices such as power bipolar transistors, silicon controlled rectifiers, ICs (CMOS, ECL, NMOS, IIL, I2L, PMOS, BiMOS), and Schottky microwave detector diodes. He is familiar with electron-beam-induced current (EBIC) and photoemission analysis techniques for locating EOS/ESD damage.
He is knowledgeable of determining the safe operating current and fusing current of both "long" and "short" wires.
Adept in electrical burnout, Expert understands bulk joule heating versus pn junction reverse breakdown heating, as well as adiabatic versus non-adiabatic processes.
Having 30 years experience in electric currents, he is conversant in Ohm's law and the relationship between electric current and magnetic field and between electric current and power.
Expert understands the causes and effects of electrostatic fields. He has measured such fields, and he knows how stray fields can be troublesome in particulate control and in ESD control in the electronics industry. In investigating manufacturing problems, he often finds electrostatic fields emanating from charged insulators such as Teflon, and he eliminates the problem with ionization.
Having 15 years experience in MOS technology, Expert has designed MOSFET (as well as bipolar) circuits and tested, failure analyzed, and evaluated MOSFET ICs. He is knowledgeable of MOSFET failure mechanisms such as gate oxide time dependent dielectric breakdown (TDDB), threshold voltage (Vt) shifts due to ionic contamination, radiation, process charging, and ESD.
During his 20 years of experience in semiconductor electronics reliability improvement, Expert gained knowledge of reliability models for common devices used in microelectronics circuits such as ICs, chip capacitors, inductors, LEDs, optocouplers, inductors, and power transistors.
Expert's work in this area includes algorithms for computing the cumulative distribution function (CFD) using a digital computer.
Expert has designed on-chip ESD protection for CMOS ICs. Recently, he wrote a design guideline for a 0.8 micron CMOS process.
Expert understands how to make ESD/hot-electron trade-offs. When self-protecting nFETs are impractical, he has used ballast resistors in series with the fingers of the output FETs to protect the output and has used separate ESD clamps to absorb the ESD transient.
Expert has more than 15 years of failure analysis experience in performing high temperature bakes and using the results to distinguish between charged device model (CDM) type degradation and other types of electrical overstress damage. He has used this technique to identify ionic contamination, gamma ray and beta particle degradation, and hot-electron degradation caused by reverse avalanching the base-emitter junction of bipolar transistors.
Having studied diode breakdown voltage for most of his career, Expert has expertise in the underlying semiconductor physics responsible for breakdown. This includes an understanding of the effects of doping concentration; impact ionization; temperature; neutron, gamma, and beta radiation; depletion layer thickness; surface effects; and crystal imperfections such as stacking faults and dislocations. He is familiar with zener breakdown and avalanche breakdown.
Expert has 15 years experience working with semiconductor devices that exhibit conductivity modulation. He understands how conductivity modulation improves the performance of forward biased ESD clamping diodes by reducing their series resistance; he also knows how this mechanism results in high current beta fall-off of power transistors.
Proficient in the physical mechanisms responsible for SEU soft errors, Expert knows how package alpha particles and neutrons, protons, pions, and muons from cosmic rays cause sea level SEU.
Expert has used lognormal life distributions to forecast failure rate of semiconductor devices. He is familiar with methods for evaluating lognormal functions and for extracting lognormal parameters from experimental data.
Proficient in the methods of predicting reliability of plastic encapsulated microcircuits, Expert has a thorough understanding of the Peck Equation and HAST for ensuring reliability of plastic parts.
Expert uses the lateral extent of discoloration in CMOS and bipolar ICs to differentiate between EOS and ESD. Also, he understands how discoloration on the surface of ICs can be interpreted for failure analysis to give information about the time duration (pulse width) of the EOS event.
Most of Expert's work involves semiconductor diodes including pn junction and Schottky diodes. He is familiar with recovery time of pn diodes, breakdown voltage, minority carrier lifetime, thermal resistance, instabilities, temperature and radiation effects, gold doping, and failure mechanisms.
Expert understands the conduction of heat in solids and has used thermal analysis in his work for the past 15 years. He is familiar with thermal resistance, thermal diffusion length, and the role of eutectic temperature in ESD contact damage.
Expert is adept in electrostatic induction and triboelectric charging and how it can cause manufacturing fallout in the semiconductor industry. He uses an E-field meter or an electroscope to survey the work area for stray E-fields. He uses a portable radio receiver to detect the EMI produced by the ESD spark and a Faraday cup to measure charge.
Expert has used SPICE models for HBM and CDM current pulses to design on-die ESD protection circuits. These designs include BIGFET clamps and avoid the use of snapback devices and reverse avalanching diodes. He is knowledgeable of SPICE circuit models for ESD diodes that properly characterize the diode series resistance.
SILICON COMPONENT RELIABILITY. Part of Expert's work in this area includes quantifying reliability in terms of wafer yield, test fault coverage, voltage, die area, burn-in, and IDDQ test metrics.
DOUBLE DIODE ESD PROTECTION. Expert has used double diodes in conjunction with Worley BIGFETs to design ESD protection without snapback devices and avalanching junctions.
GROUNDED GATE NFET SNAPBACK ESD CLAMP. Expert has dealt with the problem of non-conducting fingers. He understands that the drain contact to gate spacing should be about the same length as the thermal diffusion length corresponding to the particular ESD pulse, that most devices have holding voltages, Vh, in the 6 to 8 volt range, and that permanent damage will result when the current exceeds the second breakdown current, It2.
GATE-COUPLED NMOS (GCNMOS) SNAPBACK ESD CLAMP (GCNMOS). The GCNMOS device exhibits a negative resistance, low impedance "snapback" I-V behavior and is useful for clamping ESD voltage to nondestructive levels. Expert has selected the value of the RC time-constant which is a critical parameter in the design of the device.
WHOLE-DIE CLAMP ESD PROTECTION SCHEME. Expert wrote a procedural guide for designing with the whole-die clamp, also known as the Merrill clamp and the Worley BIGFET clamp.
He wrote design guideline for on-chip ESD protection for a 0.8 um CMOS Digital CMOS Process. This 70 page document was written for a Fortune 500 company.He provided one-day on-site consultation for small silicon-valley fab-less company to resolve ESD related crisis.He wrote application note for Fortune 500 company that related the ESD performance of an IC to safe current levels from automatic testing.He provided one-day seminar on "How to safely handle ESD sensitive components."He provided one-site consultation for major aerospace company to resolve high failure rates associated with assembly of class 0 ESD ICs.
Expert may consult nationally and internationally, and is also local to the following cities: Phoenix, Arizona - Tucson, Arizona - Mesa, Arizona - Glendale, Arizona - Scottsdale, Arizona - Chandler, Arizona - Tempe, Arizona - Gilbert, Arizona - Peoria, Arizona
|Year: 1970||Degree: PhD||Subject: Electrical Engineering||Institution: University of Tennessee|
|Year: 1968||Degree: MS||Subject: Electrical Engineering||Institution: University of Tennessee|
|Year: 1966||Degree: BS||Subject: Electrical Engineering||Institution: University of Tennessee|
|Years: 1991 to 2007||Employer: Medtronic, Inc.||Title: Senior Staff Scientist||Department: IC Design||Responsibilities: He participated in the development of ESD protection structures for all IC technologies used at Medtronic. He also participated in research and application of device physics as it relates to product reliability, overstress testing, single-event upset, ESD in manufacturing, and other related areas.|
|Years: 1984 to 1991||Employer: Raytheon Company||Title: Principal Engineer||Department: Reliability Analysis||Responsibilities: He provided resolutions to a broad range of reliability issues. Consultated in areas of physics of failure, device reliability, and IC design.|
|Associations / Societies|
|He is a member of IEEE, ASM, ASTM, APS, ESD Association, and JEDEC.|
|Licenses / Certifications|
|He was the Technical Program Chairman of ASM International Symposium for Testing and Failure Analysis (ISTFA).|
|Awards / Recognition|
|He was awarded ISTFA Best paper award for a publication on operating microelectronic bonding wires. He is also the recipient of numerous Medtronic awards.