Intellex Acquires Expert by Big Village

We're thrilled to announce that Intellex has acquired Expert by Big Village, effective March 22, 2024. This strategic move enhances our capabilities and strengthens our commitment to delivering exceptional solutions to our customers.

Stay tuned for more updates on how this acquisition will benefit our clients and experts.

For inquiries or more information, please contact us at info@intellex.com.

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Expert Details

IC Substrate Manufacturing, Chemical Vapor Deposition, Phenomenological Thermodynamic Modeling

ID: 727799 California, USA

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Expert owned the copper plating process module at Intel's Assembly Test Technology Development site for ~2 years, focusing on plating deposition process, plating solution chemistry, plating equipment and thickness uniformity control as pertaining to IC substrate manufacturing. He interfaced with plating solution and equipment suppliers, as well as substrate manufacturers, to push the state of the art for both electroless and electrolytic copper plating. His work involved selection and implementation of new unfilled and filled via plating chemstries, periodic reverse pulse plating equipment, jet plating equipment, and continuous plating equipment for panel-level plating. His work also included periodic troubleshooting of high volume manufacturing lines to resolve electrolytic plating issues, which included bubble entrapment, via delamination, and large dimple formation, as well as electroless plating issues such as incomplete via coverage, thickness non-uniformity across the panel, and foreign material induced quality issues.

He provided consulting expertise to a company building MEMS-type devices consisting of a sequential build process which suffered from a corrosion issue. Provided a detailed review of potential sources of corrosion, and proposed a corrective action plan to address the issues.

Education

Year Degree Subject Institution
Year: 2004 Degree: PhD Subject: Chemical Engineering Institution: University of Florida
Year: 1997 Degree: Bachelor's Subject: Chemical Engineering Institution: Georgia Institute of Technology

Work History

Years Employer Title Department
Years: 2016 to Present Employer: Undisclosed Title: Principal Microelectronic Packaging Engineer Department:
Responsibilities:
Microelectronic packaging engineer developing breakthrough data-center switch technology to increase bandwidth and reduce cost.
Years Employer Title Department
Years: 2008 to Present Employer: Undisclosed Title: Director, Engineering Department:
Responsibilities:
Director of Engineering leading substrate and advanced packaging teams
Years Employer Title Department
Years: 2004 to 2008 Employer: Intel Corporation Title: Senior Packaging Engineer Department: Assembly Test Technology Development
Responsibilities:
Packaging engineer focused on substrate module (surface finish, Cu plating, core material and buildup dielectric material selection, halogen-free conversion)
Years Employer Title Department
Years: 1999 to 2004 Employer: University of Florida Title: Graduate student Department: Department of Chemical Engineering
Responsibilities:
MOCVD of thin film diffusion barriers (WNxCy), epitaxy buffer layers (BP), and high brightness electron sources (LaB6). Thermodynamic analysis of a 5-component W-N-H-C-Cl system.
Years Employer Title Department
Years: 1997 to 1999 Employer: Fluor Daniel, Inc Title: Associate Process Engineer II Department:
Responsibilities:
Chemical engineer supporting design and fabrication of manufacturing plants, including DuPont acrylic resin, DuPont automotive paint, and GE polycarbonate facility expansions.

International Experience

Years Country / Region Summary
Years: 2008 to 1915 Country / Region: Asia-Pacific Summary: He defines the substrate technology roadmap for a Fortune 500 company, and is driving substrate manufacturing technology upgrades and implementation to production at a number of substrate manufacturing sites in Asia. He also drives assembly material selection and process improvements at a number of large asubcontractor sites in Asia.
Years: 2004 to 2008 Country / Region: Japan Summary: Working with major FCBGA/FCPGA/FCLGA substrate suppliers, he drove implementation of new ENEPIG surface finish onto substrates used in HVM by a major worldwide semiconductor producer. He also drove technology development for copper plating (to improve thickness uniformity), led halogen-free substrate materials selection and implementation, and led a warpage improvement effort for said major worldwide semiconductor producer.

Career Accomplishments

Associations / Societies
-iNEMI
-iMAPS
-AICHE
Professional Appointments
-Former co-chair of iNEMI surface finish consortium
-Session chair for iMAPs "Think Thin" workshop
Awards / Recognition
-Invited guest lecturer to ASU's Introduction to Microelectronic Packaging Course
-Invited speaker at Intel/Halogen Free Symposium
Publications and Patents Summary
He has 27 patents issued by the USPTO, and over 10 publications.

Additional Experience

Training / Seminars
Regularly teach a half-day class on IC substrate manufacturing at Qualcomm. Have also taught similar class at Arizona State University as a guest lecturer.
Vendor Selection
Expert has significant experience in choosing, vetting, and qualifying suppliers for substrate manufacturing, MLCC capacitor manufacturing, core/prepreg manufacturing, solder resist manufacturing, and assembly manufacturing.
Marketing Experience
Expert lead development of Qualcomm's substrate roadmap, which is the model for FCCSP development in the industry. He also collaborated on Qualcomm's overall packaging roadmap, which is a model for packaging in the mobile space. He has significant industry network, and remain apprised of key developments on regular basis.
Other Relevant Experience
Expert can provide consulting on substrate manufacturing yield improvements, warpage improvements, roadmapping, and assembly technology troubleshooting.

Language Skills

Language Proficiency
French He can speak, read and write French at an intermediate level, having studied for 4 years in high school and 1 year at University level.
Portuguese He can speak, read and write Brazilian Portuguese at an intermediate level, having traveled substantially to Brazil from 2002 to present day.

Fields of Expertise

copper metallizing, interconnect substrate, metal organic chemical vapor deposition, printed circuit board substrate, surface finishing process, atomic layer deposition, film surface treatment, thin-film electromigration, printed circuit board material, chemical vapor deposition reactor, surface characterization, electronic packaging technology, depaneling, plastic substrate, chip-to-package interconnection, chemical vapor deposition precursor material, printed circuit board drilling, four point probe, hybrid microelectronic device, dielectric coating, base metal (plating/cladding), warpage, low-pressure chemical vapor deposition, copper etching, interconnection technology process development, adhesion promoter, via, electronic material, vacuum metallizing, metal to plastic adhesion, semiconductor assembly engineering, surface finish property, printed circuit board manufacturing, printed circuit board laminate, printed circuit board assembly process, printed circuit board, electrochemical metal etching, thin-film deposition, electroplating, finishing material, finishing, integrated circuit assembly, substrate, thin film, thin-film circuit, thick film, semiconductor metallizing, plating process, metallizing, metal finishing process, chemical vapor deposition

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