Expert Details
Low Power Chip Design, Verification, DSP, and Algorithms
ID: 725847
Texas, USA
He has worked as designer on x86 and Texas Instruments DSPs. He has consulted extensively on SOC power management architecture design and validation. He teaches graduate level courses on Computer Architecture, Microprocessor Design, and Digital Logic Design at universities.
He has led technology development roles at EDA startups Verisity (acuired by Cadence), ArchPro (acquired by Synopsys), and Atrenta. While working for these companies, he has consulted with Semicondcutor companies such as Texas Intruments, Intel, QualComm, Broadcom, ST Microelectronics, Infineon, and several starups on design and validation of low power chips.
He has a PhD in the area of Computer Science and a leading expert in design and development of algorithms including parallel algorithms.
He has trained several companies in the area of fault-tolerant hardwrae and software design. He also teaches graduate-level courses on fault-tolerant computing. He is intimately familiar with fault-tolerant software development and asscoiated techniques. He has worked on adding fault-tolerance to integrated circuits.
He has trained several companies in the area of fault-tolerant hardwrae and software design. He also teaches graduate-level courses on fault-tolerant computing. He is intimately familiar with fault-tolerant and reliable software development and asscoiated techniques. He has worked on adding fault-tolerance to design highly reliable integrated circuits.
He helped develop software for verification of low power designs that use power management techniques. He helped improve power efficiency of DSP Algorithm implementation. He trained employees on power management techniques and their design and verification implications. He trained employees on fault-tolerant design techniques for hardware and software. He consulted on efficient algorithm for security implementation.
Education
| Year | Degree | Subject | Institution |
|---|---|---|---|
| Year: 1994 | Degree: PhD | Subject: Computer Science | Institution: SMU |
| Year: 1990 | Degree: MS | Subject: Computer Science | Institution: SMU |
| Year: 1987 | Degree: BS | Subject: Electrical Engineering | Institution: Indian Institute of Technology, Kanpur |
Work History
| Years | Employer | Title | Department |
|---|---|---|---|
| Years: 2007 to Present | Employer: Undisclosed | Title: Consultant/Owner | Department: |
Responsibilities:He consults with Semicondcutor Companies in the area of low power chip design and verification. |
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| Years | Employer | Title | Department |
| Years: 1996 to Present | Employer: Undisclosed | Title: Adjucnt Professor | Department: Computer Science and Engineering |
Responsibilities:He taught courses on VLSI Design, Computer Architecture, Algorithms, Fault Tolerant Computing, Microprocessor and Digital Logic Design. |
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| Years | Employer | Title | Department |
| Years: 2001 to 2006 | Employer: Atrenta | Title: Technology Director | Department: R&D |
Responsibilities:He led the development of low power software (SpyGlass LP) for the company that became one of the key products of the company. |
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| Years | Employer | Title | Department |
| Years: 1987 to 1999 | Employer: Texas Instruments | Title: Member of Technical Staff | Department: R&D |
Responsibilities:He led various DSP related R&D projects at the company with focus on low power design and verification. |
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International Experience
| Years | Country / Region | Summary |
|---|---|---|
| Years: 2008 to 2008 | Country / Region: India | Summary: He trained employees on power management technqiues for low power design. |
| Years: 2005 to 2005 | Country / Region: Europe (France, Germany) | Summary: He helped validate cell-phone chip designs that used low power techniques. |
Career Accomplishments
| Associations / Societies |
|---|
| Senior Member, IEEE Member, ACM |
| Professional Appointments |
|---|
| General Chair, IEEE Electronic Design Process Symposium Vice President, IIT Kanpur Alumni Association |
| Publications and Patents Summary |
|---|
| He has over 30 IEEE/ACM publications at various conferences and journals; He is the author of 5 issued patents and 1 pending in the area of low power chip design. |
Additional Experience
| Expert Witness Experience |
|---|
| He worked with corporate lawyers on technology patents issues at Texas Instruments. |
| Training / Seminars |
|---|
| He has presented at over 30 IEEE/ACM conferences, most recently at this year's (2008) ARM Developer's Conference and at the IEEE ICCD Confernce. |
| Vendor Selection |
|---|
| In leading technology development roles at his previous jobs, he has helped secure vendors/suppliers in hardwrae and software design areas. |
| Marketing Experience |
|---|
| He has been in the Semiconductor Industry for over 20 years now and have followed several comapnies in the industry for many years. This is to keep track of fast changing technology in the industry. |
| Other Relevant Experience |
|---|
| He's an expert in several hardware and software programming languages; this knowledge come very handy in consulting services in the Semiconductor Industry as the design goes through a series of changes, described in languages at various levels of abstraction, all the way to the manufacturing step. |
Language Skills
| Language | Proficiency |
|---|---|
| Hindi |
Fields of Expertise
bus architecture, computer hardware design, integrated-circuit design, integrated circuit, computer architecture, computer processor architecture, high-performance computing, integrated circuit selection, parallel processing, computer system, electronic design automation, computer-aided integrated-circuit design, computer simulation, integrated-circuit design software, computer science, concurrent software, computer programming, computer programming, fault-tolerant computer system, fault tolerance, fault tolerant, fault-tolerant architecture, computer reliability prediction, architectural design, direct simulation monte carlo, bluetooth, computer networking patent, concurrency (computers), statistical computing, network reliability, personal computer architecture, custom integrated circuit, failure rate, integrated-circuit reliability, UNIX system administration, embedded system software development, floating-point processor, STD bus, local bus, computer clock rate, Power PC microprocessor, PowerPC/601, computer benchmark, computer networking, computer analysis, embedded software, array processor, computational method, computer network standard, computation, embedded processing, computer system reliability improvement, fault-tolerant computer, neural networking, multibus, iterative method, local-area network management, Ethernet Network, distributed computing technology assessment, massively parallel computer system, parallel computer processing, computer data communication protocol, input/output software, computer processing, natural language text processing, computer graphics process, reduced-instruction-set computing, computer communication, data transmission, hybrid integrated circuit design, embedded computer system, client/server architecture, systolic architecture, data bus, computer graphics, computer technology, computer, semiconductor device, parallel computer architecture, number crunching, networking, semiconductor mask, network, computer network, computer interface, communication software, artificial intelligence