Expert in Microelectronics, Nanotechnology, Semiconductors, Memory
Expert has covered the entire gamut from intrinsic through low-doped to highly doped semiconductor materials as part of his professional experience. As a yield engineer at Intel Corporation, he provided advice to a wide range of process modules about efficiency improvements based on data analysis of semiconductor devices involving different kinds of doped layers. He has also provided expert internal advice about polarization-based devices with mobile charges in undoped semiconductors as they pertain to epitaxial layer selection as a senior process engineer at Global Communication Semiconductors. One of the major thrusts of his past research was to understand the low ionization ratios due to large activation energies of acceptors in wide band-gap semiconductor materials, and to device innovative approaches to achieve desirable device performance despite this technological difficulty. He has also worked on the effect of built-in electric fields and of spontaneous and piezoelectric polarization on dopant properties inside quantum wires. One of the devices he worked on required a deep understanding of p-type and n-type behavior of semiconductor materials. He has published articles in journals and conference proceedings and he has also filed a provisional patent related to these areas. He has also done fabrication and characterization work in order to explain the properties of n-type and p-type semiconductors as they pertain to novel device structures. The formation and the properties of semiconductor inversion layers and two-dimensional electron or hole gases has also been part of Expert's research and development portfolio.
As a researcher at the Cornell Nanofabrication Facility in Ithaca, NY and at the University of Utah in Salt Lake City, UT, Expert has worked on a wide range of devices. While working as a senior process engineer at Global Communication Semiconductors, he has provided advice on selection of epitaxial layers from different vendors in order to achieve device goals. As a yield engineer at Intel, Santa Clara, different kinds of solid-state transistors were some of the devices he considered while providing advice to process engineers about streamlining production operations. He has fabricated a new class of solid-state rectifiers involving ultra-thin nano-layers of Aluminium Gallium Nitride, where the spontaneous and piezoelectric polarizations have been exploited to engineer device properties. He has also built and tested electromechanical solid-state switches for potential harsh-environment applications. He has done investigations into current flow mechanisms in polarization barriers involving quantum mechanical tunneling, drift and diffusion. These novel barriers using wide band-gap semiconductors can potentially serve as high-power microwave switches for signal processing in a range not covered by other semiconductors.
Expert has wide-ranging experience in the simulation and modeling of semiconductor devices and properties. Moreover, as a staff device engineer at SanDisk Corporation, he has provided extensive advice to the company's device team about the capabilities of simulators, and he has provided advice about device capabilities and scaling limitations based on state-of-the-art simulations. He also brought his knowledge of semiconductor devices to bear on efficiency imporvement efforts in Intel Corporation's NOR flash memory division in Santa Clara, CA while working as a yield engineer there. He used statistical analysis of relevant device parameters to advice a wide range of process engineers about modifications to process flows. He has used both commercial simulators and hand-written codes to model a large variety of device structures. He has worked closely with Silicon Valley commercial simulator vendors to incorporate new physical effects into device simulation. He has also written Matlab code to encompass novel materials properties that were not part of commercial simulators at that time. He has published extensively related to the physics of charge transport across semiconductor and semiconductor-metal barriers. He has worked on the incorporation of important quantum mechanical effects into device behavior in a wide range of device structures. A lot of Expert's prior work has focused on obtaining an understanding of experimental results using cutting-edge theoretical knowledge.
Expert has close to 10 years of experience related to device testing and characterization. As a yield engineer in Intel Corporation's NOR flash memory division, he has provided advice to different process engineering modules in Intel, Santa Clara about efficiency improvement based on electrical test data collected on semiconductor devices. He has characterized a wide range of semiconducting and other kinds of materials for device applications. He has dealt with test data collected in manual, semi-automated and automated fashions. He has performed and provided advice on DC, AC and pulse testing of semiconductor devices. He has also worked on streamlining testing procedures at Intel Corporation. His work has often focused on gaining the best understanding of device or circuit data using theoretical capabilities.
While working as a yield engineer at Intel, Expert gave expert advice to different departments inside Intel Corporation's NOR flash memory division at Santa Clara about semiconductor device data, and their relevance to different aspects of Intel, Santa Clara's production line. He has used his device expertise and his statistical expertise to guide process engineers in Intel's NOR flash memory division to implement cost-cutting measures and process improvements based on semiconductor device data. He has also evaluated and given expert advice at SanDisk Corporation pertaining to software selection for simulation of non-volatile memory structures while working as a staff device engineer in the company. He has worked on a wide range of devices like heterojunction bipolar transistors, high-electron mobility transistors, polarization barriers, non-volatile memory switches and nano-electromechanical devices. While a large part of his work has dealt with discrete semiconductor devices, he also has dealt with integration issues related to several of these devices. As a researcher at the Cornell Nanofabrication Facility and at the University of Utah, he fabricated and characterized several novel classes of devices. As an engineer at Intel Corporation, SanDisk Corporation and Global Communication Semiconductors, he has worked on cutting-edge device issues pertaining to several different semiconductors. His publications have dealt with a number of semiconductor devices and about advancing the state-of-the-art in several areas of semiconductor electronics.
Expert has advised several different process modules in Intel Corporation's NOR flash memory division about implementation of cost-cutting measures and efficiency improvements. In the process, he brought his semiconductor and statistical expertise to bear on significant aspects of semiconductor device manufacturing and semiconductor technology and their impact on product costs while working as a yield engineer there. He has also provided expert internal advice regarding the suitability of simulators from Silicon Valley vendors for the design of next-generation devices and products as a staff device engineer at SanDisk Corporation. He has used a wide array of fabrication techniques and equipments to do cutting-edge research and development work in semiconductor and solid-state devices. Some of the techniques he has used as part of his work are photolithography, electron beam ( E-beam ) lithography electron cyclotron resonance ( ECR ) plasma etching reactive ion etching, inductively coupled plasma etching, evaporation sputtering, chemical vapor deposition oxidation, diffusion doping, scanning electron ( SEM ) microscopy EDAX ( Energy Dispersive X-Ray ), ellipsometry and atomic force microscopy. He has wide-ranging knowledge of the interactions between processing, testing and quality control aspects of product development and manufacturing.
Served as internal expert for evaluating device simulation software for SanDisk Corporation. Cutting-edge finite-element softwares were evaluated for use in the research and development activities geared towards exploratory memory cells. New physical effects and models were evaluated, and cost-benefit anaysis of incorporation of physical models of different levels of intricacy were done. Expert interacted extensively with Silicon Valley commercial device simulation software providers, and provided expert internal advice about the different softwares.Served as internal expert for deciding high electron mobility transistor epi layers for Global Communication Semiconductors. Expert used his prior knowledge of compound semiconductors to do cost-benefit analysis based on device goals and vendor offers.Served as internal expert for key cost-cutting activites at Intel Corporation's NOR Flash memory division in Santa Clara, California. Expert provided extensive advice to a wide array of process engineers based on statistical analysis, device knowledge and product requirements. He also undertook an analysis of electrical testing procedures with a view to implementing streamlining of existing testing paradigms. Some of the examples of efficiency improvement or process improvement measures he was involved with are as follows.
1. Used statistical analysis to find root cause of process deviations at Intel’s Santa Clara factory
a. Did statistical analysis of electrical parameters to find aberrant tools in the production line
b. Used statistical analysis to detect ion-implanter that was causing shift in process, as well as to detect the effect of certain process changes on the health of the line
c. Used statistical correlation between electrical parameters to help process engineers detect problematic process sequence causing a certain type of transistor to not function within specifications
d. Used statistical correlation between electrical parameters to help process engineers detect problematic process sequence causing a certain type of oxide thickness be outside specified limits
2. Used statistical analysis to study the possibility of cost-cutting in Intel’s Santa Clara factory by eliminating certain electrical tests
3. Used statistical analysis of electrical data to help different process engineers in Intel’s Santa Clara factory to evaluate and implement cost-cutting measures in the process line
Expert may consult nationally and internationally, and is also local to the following cities: San Jose, California - San Francisco, California - Sacramento, California - Oakland, California - Stockton, California - Fremont, California - Modesto, California - Salinas, California - Santa Rosa, California - Hayward, California
|Year: 2004||Degree: PhD||Subject: Electrical Engineering||Institution: Cornell University|
|Year: 2000||Degree: Master of Science||Subject: Electrical Engineering||Institution: Cornell University|
|Year: 1997||Degree: Bachelor of Technology||Subject: Electrical Engineering||Institution: Indian Institute of Technology|
|Years: 2009 to 2009||Employer: Global Communication Semiconductors||Title: Senior Process Engineer||Department: Technology||Responsibilities: 1. Characterization of Aluminium Gallium Nitride high electron mobility transistors
2. Design of Aluminium Gallium Nitride high electron mobility transistors ( Expert evaluated different epi-layer designs to achieve product goals. Trade-offs between different device parameters, and the way they are affected by epitaxial layers were key components of the analysis performed by him to arrive at optimal solutions )
|Years: 2007 to 2009||Employer: SanDisk Corporation||Title: Staff Device Engineer||Department: Device Integration||Responsibilities: 1. Characterization of a wide array of non-volatile memory devices
2. Simulation of non-volatile memory devices
( Expert worked on the characterization and modeling of several innovative approaches to overcoming scaling limitations in non-volatile memory cells. While a lot of his work focused on the discrete device, he also studied the thermal and electrical effects of one memory cell on neighboring memory cells. He worked on optimizing device performance with a view to meeting product goals for scaled technology nodes. Some of the approaches he worked on were very futuristic, and involved advanced technological tricks. He also used his characterization and theoretical expertise to arrive at an understanding of microscopic and macroscopic mechanisms in exploratory memory cells. He interacted intensively with research and development entities outside the company to arrive at the best solutions for the company's non-volatile memory roadmaps and visions. He worked on a wide range of electrical testing techniques like steady-state and transient testing to arrive at carrier transport mechanisms, switching mechanisms and device constraints )
|Years: 2005 to 2007||Employer: Intel Corporation||Title: Yield Engineer||Department: Yield||Responsibilities: 1.Etest and Yield Analysis of Flash Memory technologies
2.Etest data analysis for process improvements of flash products
3. Root cause analysis for line yield improvement of flash products
( Expert used device analysis methods and statistical methods to ensure high yields in Intel Corporation's NOR Flash memory line in Santa Clara, Caifornia. He also brought his expertise to bear on the development of new flash memory products. He worked closely with several process teams to identify, highlight and solve product marginality issues and sensitivity of the product to different process segments. He undertook efforts to streamline testing procedures, and also worked with process teams to make Intel's NOR Flash memory line more efficient. )
|Years: 2009 to 2009||Employer: University of Utah||Title: Postdoctoral Research Fellow||Department: Electrical and Computer Engineering||Responsibilities: 1. Fabrication and characterization of Nano Electro Mechanical Structures for possible non-volatile memory applications
( Expert fabricated and characterized advanced nano-electromechanical switches with low switching voltages, and potentially fast switching. The switches he worked on can also have potential uses in harsh-environment electronic applications. )
|Years: 1998 to 2003||Employer: Cornell University||Title: Graduate Research Assistant||Department: Electrical and Computer Engineering||Responsibilities: 1. Design, fabrication and characterization of AlGaN/SiC heterojunction bipolar transistors with emphasis on understanding carrier transport across the AlGaN/SiC heterojunction and optimization of DC characteristics
2. Design, fabrication and characterization of polarization barriers based on Aluminium Gallium Nitride and Gallium Nitride heterojunctions. Related experimental device characteristics with fundamental material properties, especially spontaneous and piezoelectric polarizations
3. Modeling of hole transport across Indium Gallium Nitride cap layers on Aluminium Gallium Nitride for enhanced tunneling probabilities and improved ohmic contact resistances
4. Cornell Nanofabrication Facility (CNF)
Design, Fabrication and Characterization of Wide Band Gap Semiconductor Devices.
( a ) GaN/SiC Heterojunction Bipolar Transistors
( b ) AlGaN/GaN Polarization Barriers
( Expert worked on different experimental and theoretical aspects of wide band-gap compound semiconductors. His workfocused on the optimization of device characteristics for potential high-power high-frequency microwave applications. He worked on the utilization of spontaneous and piezoelectric polarization effects to obtain enhanced performance in some devices, and on ways to mitigate deleterious effects of features like high acceptor ionization energies using polarization-induced charges )
|Associations / Societies|
|Institute of Electrical and Electronic Engineers,
Materials Research Society
|Co-chair of Device Analysis Team at Intel Corporations's NOR Flash Memory division in Santa Clara|
|Awards / Recognition|
|Certificate of appreciation from Intel Corporation for work on non-volatile memory products.|
|Publications and Patents Summary|
|ExpertPraharaj has published in international journals and international conference proceedings like Solid State Electronics, Micro and Nano Letters, Proceedings of the Materials Research Society and the Device Research Conference. His publications deal with both experimental and theoretical issues related to solid-state devices, especially in the area of semiconductors. (PUBLICATIONS AND PRESENTATIONS
1. GaN/SiC Heterojunction Bipolar Transistors,W J. Schaff, H.Wu, C.J.Expert, M.Murphy, T.Eustis, B.Foutz, O.Ambacher and L.F.Eastman, Solid State Electronics, Volume 44, No 2, 2000
2. Asymmetrical Current Conduction across a 50 angstroms thick Aluminium Gallium Nitride Polarization Barrier C.J.Expert, J. Hwang and L.F.Eastman Micro and Nano Letters, 2006
3. Enhanced Tunneling through sub 30 Angstroms thick Gallium Nitride Cap Layers on Silicon Carbide for Low Contact Resistance, C.J Expert, Proceedings of the MRS Spring Meeting, 2007
4. Effect of Strain and Polarization Grading on Hole Transport across Tunneling Barriers between Metals and Wurtzite Indium Gallium Nitride, C.J Expert, Proceedings of the MRS Spring Meeting, 2007
5. Effect of Spontaneous and Piezoelectric Polarization on the Base Resistance and Frequency Response of AlGaN/SiC Heterojunction Bipolar Transistors, C.J Expert, Proceedings of the MRS Spring Meeting, 2008
6. Donor binding energies in rectangular wurtzite Aluminium Gallium Nitride / Gallium Nitride quantum wires with spontaneous and piezoelectric polarization, C.J Expert, Proceedings of the MRS Spring Meeting, 2008
7. Electron Energy Spectra of Single and Multiple AlGaN/GaN Quantum Dots with Spontaneous and Piezoelectric Polarization Effects, C.J Expert, Proceedings of the MRS Spring Meeting, 2007
8. Optical Absorption at Digitally and Continuously Graded Indium Gallium Nitride Schottky Barriers, C.J Expert, Proceedings of the MRS Spring Meeting, 2007
9. Current voltage characteristics of an Aluminium Gallium Nitride Polarization Barrier, C.J.Expert, J. Hwang and L.F.Eastman MRS Spring Meeting, 2005 (accepted for poster session )
10. Thin Indium Gallium Nitride Caps for improved Hole Tunneling and lower Contact Resistance to Wurtzite p-type GaN, C.J Expert and L.F.Eastman, to be submitted
11. Polarization-based ohmic contacts to Aluminium Gallium Nitride using Indium Gallium Nitride cap layers, C.J. Expert and L.F.Eastman, to be submitted
1. A device to obtain tunable energy levels of impurity donors and acceptors in quantum wells and quantum wires made from group-III nitride semiconductors with wurtzite crystal symmetry using composition grading ( to be submitted )
2. An Aluminium Gallium Nitride/ Silicon Carbide heterojunction bipolar transistor with improved frequency response using spontaneous and piezoelectric polarization effects ( provisional application filed ) )
|Training / Seminars|
|Expert taught the Etest class for 65 nanometers Flash technology at Intel Corporation, Santa Clara in January 2007, and the Etest class for 90 nanometers Flash technology at Intel Corporation, Santa Clara in December 2005. Both classes helped process, quality and other engineers gain an overview of electrical testing methodologies, yield improvement efforts and root-cause analysis of deviations in the production line, all of which form crucial components of Intel's quality enhancement efforts. In these classes, Expert presented case studies from Intel's NOR flash production line as they related to overall yield and to product performance.|
|Expert has worked on extensive evaluation of state-of-the-art commercial simulator capabilities from Silicon Valley software suppliers for exploratory non-volatile memory cells. He has also worked on epi-layer selection issues for compound semiconductor devices, and evaluated pros and cons of epi-layer offers from different vendors.|
|Expert has worked on advanced issues related to non-volatile memory scaling, and the use of exploratory approaches to overcome scaling limitations in the non-volatile memory industry. His characterization, theoretical and simulation work have helped understand the limits and capabilities of novel non-volatile memory approaches as they relate to scaling limitations in the semiconductor memory industry.|
|Other Relevant Experience|
|Expert has solid-state device fabrication experience in the areas of Photolithography, Electron beam ( E-beam ) lithography, Electron Cyclotron Resonance ( ECR ) Plasma Etching, Reactive Ion Etching, Inductively Coupled Plasma Etching, Evaporation, Sputtering, Chemical Vapor Deposition, Oxidation, Diffusion Doping, Scanning Electron ( SEM ) Microscopy, EDAX ( Energy Dispersive X-Ray ), Ellipsometry and Atomic Force Microscopy. He has fabricated devices in different material systems using these techniques. His device characterization experience covers a wide range of techniques in DC, AC and pulse testing. He has done extensive investigation into carrier transport mechanisms in solid-state devices through these characterization techniques. He also has extensive device simulation and modeling experience in the areas of electro-thermal simulation of non-volatile memory devices ( using Silvaco Atlas and Synopsys Sentaurus/Medici softwares ), simulation of non-volatile memory device architecture, modeling of transport across contacts in wurtzite semiconductors and the modeling of electrical and optical properties of nanoscale device structures in wurtzite semiconductors. He has also used sophisticated statistical analysis methods and tools to analyze issues related to semiconductor memory product manufacturing.|