Expert Details

Expert in Semiconductor Packaging, SMT, Flip Chip and WLCSP assembly, failure analysis, Advanced Packaging Substrates

Expert ID: 735143 Arizona, USA

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Advanced Semiconductor Packaging, Expert Witness & Technology Due Diligence, Technology Investment Advising Dynamic Senior Engineering Manager with more than 15 years of International Semiconductor Packaging development and high-volume manufacturing of advanced IC packages for mobile, automotive and medical end applications. Industry recognized Fan-In and Fan-Out Wafer and Panel level packaging track record from technology development and deployment for manufacturing scale up to high volume production in overseas factories (Asia and Europe - Portugal). Proven Skills: • International Engineering Management • Mergers and Acquisitions • Intellectual Property Management • Technology Transfers • Flip Chip, Fan-In and Fan-Out WLCSP / SiP Applications • Solder and Cu Pillar Bumping Expertise • Flip Chip in Package Assembly • Stacked Die Packaging • Heterogeneous Integration • Sourcing of Laminate Packaging Substrates • Technology Transfer Expertise • Extensive Reliability, Metrology and FA Experience • Technology Qualification Skills • Oversight Customer Interfacing / Technical Marketing Skills • Excellent Verbal and Written Communication Skills • Organized Technical Management Skills • Packaging Cost Modeling Skills • Solid Team Leadership Skills • Self-Driven and Creative • Broad Advanced and Conventional Packaging Knowledge • Supplier Negotiation Skills • Semiconductor Packaging Technology Roadmapping / Definition • Extensive High-End Mobile Consumer Product Experience • Expert Witness in Advanced Semiconductor Packaging; Technology Due Diligence for M&A and Technology Investing

Education

Year Degree Subject Institution
Year: 1983 Degree: Masters Subject: Applied Polymer Chemistry Institution: University of Ottawa, Ottawa, Ontario, Canada
Year: 1981 Degree: Honors Bachelor of Science Subject: Biochemistry Institution: Laurentian University, Sudbury, Ontario, Canada

Work History

Years Employer Title Department Responsibilities
Years: 2017 to 2018 Employer: (Undisclosed) Title: Senior Technical Advisor / Engineering Consultant Department: Responsibilities: Engineering consulting firm specializing in Advanced Semiconductor Packaging solutions, Technology Due Diligence, Intellectual Property Management, and Expert Witness, Technology Investment

Provide consulting services to semiconductor foundries and fabless semiconductor companies to drive comprehensive advanced semiconductor packaging strategies including Fan-Out WLCSP and High-Density SiP applications. Develop strategic relationships for clients with prospective vendors and suppliers. Direct Open Innovation research and development with overseas OSAT partners to accelerate technology and product roadmaps.

Major Achievements:
• Facilitated Multek Industries acquisition by revising their PWB and Fan-Out PLP technology roadmap to update PCB product offerings and technology portfolio. Contributed to the successful completion of merger valued at $375 million.
• Prepared studies of equipment and material requirements for clients to access the Advanced Packaging market. Worked with equipment suppliers to determine specifications and requirements for Fan-Out PLP manufacturing. Supported equipment suppliers to promote sales to printed circuit board manufacturers and other Fan-Out PLP technology providers.
Years: 2016 to 2017 Employer: (Undisclosed) Title: Senior Technical Adviser Department: Responsibilities: US subsidiary specializing in interconnect technologies for Semiconductor Packaging and Medical Electronics.

Provided engineering support to US sales and marketing team for flexible and rigid-flex circuits, embedded die Fan-Out technologies, and multilayer flex circuit modules. Primary interface between US customers and Japanese R&D teams.

Major Achievements:
• Developed multi-layer flex circuit technology Fan-Out PLP embedded component technology called ChipsetTM for implantable medical electronic applications. Worked with overseas development and manufacturing teams to deploy applications resulting in more than $2M in prototyping and product qualification builds and $5 million in first-year production revenue for very high density medical electronic module applications.
• Formulated detailed technology roadmap and Open Innovation prioritization at Fujikura, Japan R&D organization. Collaborated with R&D companies to explore Plug and Play Incubator technologies.
Years: 2015 to 2016 Employer: HUATIAN TECHNOLOGY GROUP FLIP CHIP INTERNATIONAL Title: Chief Technical Officer Wafer Level Technologies Department: Responsibilities: Technology development for Wafer bumping, redistribution and wafer level packaging for internal and external licensing.

Drove technology roadmaps for a leading-edge flip chip in package applications.
Participated in Huatian Technology effort to plan and build a 200- and 300-mm bumping and WLCSP fab in Kunshan China and deployed a WLCSP back-end assembly and test facility.
Spearheaded an FCI joint venture in embedded component Fan-Out WLCSP SiP technology with Fujikura Limited based on multi-layer flex circuit interconnect technology. The technology was successfully deployed into high volume production for medical electronics applications.

Major Achievements:
• Managed planning and construction of Fan-In WLCSP and Wafer Level image sensor packaging facility with a $200 million USD budget and achieved earnings $50 million in revenue in the first full year of operation.
• Expanded company Wafer Bumping and Assembly experience by mentoring and coaching engineering and mid-level managers to accelerate technology development for the Kunshan factory. Completed factory launch within 18 months to process bare flip chip and Fan-In and Fan-Out WLCSP production.
• Streamlined IP and technology to minimize external counsel cost resulting in more than $1 million in savings annually. Achieved 60% cost containment resulting in lower IP related expenses to less than $750,000 annually.
Years: 2006 to 2015 Employer: FLIP CHIP INTERNATIONAL Title: Chief Technical Officer Department: Responsibilities: US-based wafer and WLCSP bumping facility.

Established product roadmap and technology priorities for internal production and for licensing to OSAT licensees. Managed wafer bumping Process R&D at FCI – Phoenix and at MMS Joint Venture in Shanghai, China.
Operations management responsibility for FCI’s WLCSP back-end processing facility in Tempe, Arizona.

Major Achievements:
• Expanded FCI’s Cu WLCSP and Flip Chip product line to increase revenues by $4 million annually.
• Led technology licensing and transfer efforts to develop and maintain a portfolio of wafer bumping, WLCSP, and Cu pillar bumping patents. Developed revenues of more than $75.2 million over 10 years.
• Introduced thick copper-based process for thin and thick film electroplated Cu in support of high power and fine pitch processing capabilities.
• Participated in venture capital funding efforts including FCI’s acquisition by a Chinese OSAT. Facilitated TSHT acquisition resulting in a $45 million sale of FCI-Phoenix and Singapore Joint Venture factories.
Years: 2002 to 2006 Employer: STATS / STATSCHIPPAC Title: Senior Director, Wafer Level Technologies Department: Responsibilities: The company providing wafer bumping, wire bond and flip-chip BGA assembly, 3D, and array packaging services.

Directed deployment of FCI's wafer bumping and WLCSP technologies at a STATSChipPAC facility in Singapore. Oversaw customer flip chip bumping and assembly needs and technical sales support.

Major Achievements:
• Launched $100 million per year high volume production of wafer bumping and WLCSP bumping assembly for the Singapore facility.
• Marketed wafer bumping and back-end wafer probe and assembly manufacturing to grow revenue levels to more than $25 million annually within two years of factory completion.
• Served on Emerging Technology Teams to improve customers' product quality and reliability. Developed improvements to product quality and capability to increase customer satisfaction and position company for a merger.
Years: 2000 to 2002 Employer: AMKOR TECHNOLOGY Title: Vice President, Emerging Products Department: Responsibilities: Semiconductor product packaging and test services provider.

Led a 12-member team reviewing semiconductor packaging projects and establishing priorities. Defined packaging needs for strategic customers to prepare production factory roadmaps.


Major Achievements:
• Created stacked die memory packaging to address space issues within smartphones. Managed packaging technology development for Asian factories and programs. Established adoption of industry’s first stacked die packaging for high volume production for Intel in less than 12 months. Built first-year production levels of more than 100 million units increasing production to over 200 million units annually in overseas factories.
• Managed technology transfer of Texas Instrument’s MEMS projection technology (DLP) to a high-volume factory in Taiwan including a class 10 assembly facility. Production launched within 12 months driving initial assembly yields of 40% to more than 85% after transfer.
• Developed Wafer Level Packaging Technology by licensing and deploying FCI's WLCSP packaging technology within a high-volume production factory in Korea. Implemented WLCSP bumping capability within a pre-existing printed wafer bumping facility, establishing the company as the industry's largest WLCSP service provider.
• Directed technology transfers to high volume factories in Asia. Deployed technology to multiple worldwide factories with a 100% success rate.

Career Accomplishments

Associations / Societies
AFFILIATIONS:
Senior Member, Institute of Electrical and Electronics Engineering
Senior Member, International Microelectronics Assembly, and Packaging Society
Awards / Recognition
IMAPS John A. Wagnon Technical Achievement Award

Fields of Expertise

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