Expert Details
Integrated Circuit Fabrication and Integration
ID: 739813
Florida, USA
Core competencies include: Process Step Developments in Deposition, Oxidation, Diffusion, Electrical Test/Evaluation for Silicon Integrated Circuits, MOS, NMOS, PMOS, CMOS, Bipolar, BiCMOS, DRAM, SRAM, ROM, PROM, EPROM, logic, analog. Process Integration Development for the same list of technologies and including lithography, etch, inspections, Wafer Fabrication for the above, with supervisory responsibilities. Additional focus on Ion Implantation processes, production and process engineering.
Education
| Year | Degree | Subject | Institution |
|---|---|---|---|
| Year: 1975 | Degree: MS | Subject: Chemical Engineering | Institution: University of California, Berkeley |
| Year: 1971 | Degree: BS | Subject: Chemical Engineering | Institution: California Institute of Technology |
Work History
| Years | Employer | Title | Department |
|---|---|---|---|
| Years: 2000 to Present | Employer: Undisclosed | Title: Director of Process Engineering | Department: Innovion Corporation |
Responsibilities:Expert works in Process Engineering for a department of an American manufacturer of optical materials and semiconductors. His department is a world leader in foundry ion implant support and service for the microelectronic industry. |
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| Years | Employer | Title | Department |
| Years: 2008 to 2009 | Employer: Spansion LLC | Title: Module Shift Manager, Lithography | Department: |
Responsibilities:Training – All process technicians cross-trained for 300mm: Coat, align, expose, bake, develop – Sokudo Coat/Bake/Develop Tracks, Tel Coat/Bake/Develop Tracks, Canon I-line and DUV Steppers, ASML DUV and Immersion Steppers CD measurement, alignment – Applied and KLA Develop Inspect Chemical Handling Preventive Maintenance Scheduling: Developed database for accurate reporting of inventory locations Developed report to identify in advance lots with incomplete specifications Developed report to give 4 day advance notice of expected inventory levels by tool. Used to schedule PMs. Developed reports to quickly group similar processes for more efficient use of tool time within the confines of a constantly changing inventory and priorities, reducing inventory backlogs from 3 days to less than a shift Maintenance – coordinating vendor contract maintenance with both internal maintenance and operations Engineering Internal and External customers Coordinated requirements of both internal and external customers Internal customers consisting of Module Development Engineering, Module Technology Development and Research, multiple Product Process Integration Development groups, External customers consisting vendors with joint use agreements and customers needing access to Immersion Lithography Tooling |
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| Years | Employer | Title | Department |
| Years: 1990 to 1991 | Employer: Silicon Valley Group/Thermco Systems | Title: Factory Advocate | Department: |
Responsibilities: Vertical Diffusion and LPCVD Furnaces -- Managing and coordinating design, manufacturing, and field service, resulting in the successful installation of the Furnaces into Motorola MOS11 and later the SEMATECH Beta Units Managed the Internal Process Engineering Training in SPC and DOE, the E10-90 audits of the equipment, communications with individual customers, efforts of Engineering, Manufacturing, Process Development, and Service |
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| Years | Employer | Title | Department |
| Years: 1987 to 1990 | Employer: General Signal Thinfilm Company | Title: Product Marketing Manager | Department: |
Responsibilities:Diffusion and Chemical Vapor Deposition Product Lines -- First Successful installation of Vertical Furnaces at IBM Burlington, resulting in repeat orders. |
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| Years | Employer | Title | Department |
| Years: 1981 to 1986 | Employer: Signetics Corp. | Title: Process Integration Manager & Process Engineering Manager | Department: MOS Technology Development |
Responsibilities: Successfully installed 2 months ahead of schedule (6 month planned) a 250A, 1.5 micron CMOS process into a Bipolar Pilot Line Fab. Developed and transferred 5 MOS processes to manufacturing in Albuquerque and Sunnyvale, CMOS EPROM, CMOS uP |
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| Years | Employer | Title | Department |
| Years: 1978 to 1981 | Employer: Microcomponents Organization | Title: Project Engineer (Group Leader) | Department: MOS Manufacturing |
Responsibilities: Diffusion – Oxidation, Anneal and Drive, Diffusion PreClean Thin Films – CVD dielectrics, polysilicon, nitride Electrical Test – Parametric Test |
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| Years | Employer | Title | Department |
| Years: 1974 to 1978 | Employer: Intel Corp. | Title: Engineer | Department: |
Responsibilities: Engineer – development of resist strip solutions for metal masks, conservation of chemical, Die Production Development – Development of Intermetal dielectric, hermetic passivation, PECVD and Fab II Process Engineer – CVD for Polysilicon, Epitaxial silicon deposition for Bipolar devices, Reliability – development of improved testing and improved dielectric dielectrics |
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Career Accomplishments
| Associations / Societies |
|---|
| Institute of Electrical and Electronic Engineering. 1974 |
Fields of Expertise
microlithography, diffusion annealing, diffusion coefficient, diffusion pump, aluminum deposition, atmospheric pressure chemical vapor deposition, chemical vapor deposition, chemical vapor deposition reactor, Epitaxial deposition, low-pressure chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, silicon dioxide chemical vapor deposition, sputter deposition, optical lithography, optical microlithography, semiconductor lithography, electrical testing, statistical process control, semiconductor wafer fabrication facility, semiconductor wafer etching, semiconductor wafer processing, semiconductor wafer mask aligner, semiconductor wafer inspection, very large-scale integration, plasma etching, plasma etching technology, microfabrication plasma etching