Expert Details
Silicon: Processing, Defects, Devices, Silicon-on-Insulator, MEMS, Nanotechnology, and Semiconductors
ID: 724376
New Jersey, USA
Expert has worked on radiation hardening of semiconductor devices since 1980. He has several patents on Rad Hardening of semiconductors.
Most of his 30-year experience pertains to silicon as a semiconductor material.
Expert has a keen and deep understanding of ion implantation, plasma etching, thermal processing, and wet processing of semiconductor materials.
He has deep expertise in properties of silicon as semiconductor material.
Expert's key knowledge includes standards, manufacturing and characterization of silicon wafers, including 300 mm wafers, and especially silicon-on-insulator wafers.
Expert fully understands in-depth etching, deposition, doping, patterning and other wafer processing steps.
Expert knows manufacturing of silicon semi-insulating substrates.
Consulting various venture capital firms on silicon-on-insulator technology, market, trends
Thin film silicon solar cells: usage of nanocrystalline silicon for mitigating Wronski effect Adapting of flat display production line for making silicon solar cells Carbon nanotubes: inexpensive manufacturing Consulted Smithsonian Institution on glass and silicon cleaning in an x-ray telescope project (2016). References available
Education
| Year | Degree | Subject | Institution |
|---|---|---|---|
| Year: 1989 | Degree: PhD | Subject: Material Science | Institution: Moscow Steel & Alloys University |
| Year: 1980 | Degree: MsEE | Subject: Electronics Engineering | Institution: Moscow Institute of Semiconductor Technology |
Work History
| Years | Employer | Title | Department |
|---|---|---|---|
| Years: 2015 to 2016 | Employer: Company in Europe | Title: Consultant | Department: |
Responsibilities:• Improved engineered wafer process to make substrates for RF MEMS• Transferred to local team wafer processing experiences specific to thin SOI – ion implant, wafer bonding, etc. |
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| Years | Employer | Title | Department |
| Years: 2013 to 2015 | Employer: SunEdison | Title: Sr Research Engineer | Department: SOI R&D |
Responsibilities:Accomplishments:• Developed novel manufacturing processes for HVM (high volume manufacturing) silicon-on-insulator and solar wafers, being patented. • Developed 300mm SOI wafer process for RF applications (handhelds and cell phones). Resulting wafers far exceed existing products in RF performance (2nd harmonic suppression). Company became first on world market with this product. |
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| Years | Employer | Title | Department |
| Years: 2008 to 2013 | Employer: Corning | Title: Sr Research Scientist | Department: R&D |
Responsibilities:Accomplishments:• invented glass surface coating making moth eye like surface topology. Resulting glass has lower reflectivity. Enormous application potential – all TV, computer, and handheld screens, solar cell cover glass, etc. • solved problems of single crystal silicon layer transfer onto glass by modifying Smart-cut process. Silicon-on-glass substrate can be used to make, say, computer integrated with display on a single sheet. • critically contributed to process of making solar silicon wafers directly from molten silicon (kerf-free) – cost of silicon substrates for solar cells can be significantly reduced • team member in a project as to add self-cleaning, fingerprint-repelling, and self-disinfecting property to face surfaces of handheld devices – potentially can be used in all next generations handheld devices. |
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| Years | Employer | Title | Department |
| Years: 2005 to 2008 | Employer: MEC Tech, Toms River, NJ | Title: Chief Scientist | Department: |
Responsibilities:- Responsible for development of process technologies for new products, and for continuing process improvements for existing products- Developed innovative solutions for fabrication of silicon-based consumable parts used in semiconductor equipment as plasma etchers, rapid thermal processing furnaces, etc. |
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| Years | Employer | Title | Department |
| Years: 2001 to 2004 | Employer: Silicon Wafer Technologies, Newark, NJ | Title: CTO | Department: |
Responsibilities:- Developed new process for fabrication of silicon-on-insulator (SOI) wafers- Prototyped SOI wafers using cleanroom facilities at NJIT, Cornell, and PennState Nanofabs - Developed system-on-a-chip process featuring compatible MEMS and CMOS parts - Patented layer transfer type SOI wafer fabrication processes |
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| Years | Employer | Title | Department |
| Years: 1997 to 2000 | Employer: New Jersey Microsystems, Newark, NJ | Title: Engineer for SOI Projects | Department: |
Responsibilities:- Developed a process for manufacturing of radiation-hardened silicon-on-insulator wafers- Participated in projects on RFID MEMS chip, MEMS gyroscope chip, MEMS surgical microknife - Simulated pixels of MEMS display chip using ANSYS software |
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| Years | Employer | Title | Department |
| Years: 1995 to 1996 | Employer: New Jersey Institute of Technology, Newark, NJ | Title: PostDoc | Department: Electrical Engineering |
Responsibilities:- Performed research project on MEMS oxygen sensor for automotive applications |
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International Experience
| Years | Country / Region | Summary |
|---|---|---|
| Years: 1992 to 1995 | Country / Region: Russia | Summary: Research Professor, Moscow University of Steel and Alloys |
| Years: 1988 to 1992 | Country / Region: Ukraine | Summary: Head of R&D Department, Rotor Enterprise, Cherkasy, Ukraine |
Career Accomplishments
| Associations / Societies |
|---|
| Member of IEEE, Materials Research Society, SPIE, Electrochemical Society |
| Professional Appointments |
|---|
| Reviewer for Semiconductor Science and Technology, Journal of Physics D, IEEE Transaction on Electron Devices, and other top professional journals in semiconductors |
| Awards / Recognition |
|---|
| Obtained SBIR Phases I, II contracts from NSF, Army, Navy, and US Ballistic Missiles. Awarded with research grants from Soros, NATO, CRDF, Fubright |
| Publications and Patents Summary |
|---|
| Published 100+ papers including top refereed journals. IEEE Transaction on Nanotechnology, Semiconductor Science and Technology, Journal of Material Science, Japanese Journal of Applied Physics, etc. Holder of 3 dozen patents |
Additional Experience
| Training / Seminars |
|---|
| Taught courses on semiconductors at Moscow Steel & Alloys Institute. PhD thesis advisor to graduate students at New Jersey Institute of Technology |
| Vendor Selection |
|---|
| Consulted the following projects: Consulting various venture capital firms on silicon-on-insulator technology, market, trends. Carbon nanotubes: inexpensive manufacturing. Thin film silicon solar cells: usage of nanocrystalline silicon for mitigating Wronski. effect. Adapting of flat panel display production line for making silicon solar cells |
| Marketing Experience |
|---|
| Managed R&D departments, 2 to 25 engineers starting from late 80's. Run hi-tech start up Company (Silicon Wafer Technologies). Member of IEEE, Materials Research Society, SPIE, Electrochemical Society. Reviewer for Semiconductor Science and Technology, Journal of Physics D, IEEE. Transaction on Electron Devices, and other top professional journals in semiconductors |
| Other Relevant Experience |
|---|
| Published 100+ papers including top refereed journals – IEEE Transaction on Nanotechnology, Semiconductor Science and Technology, Journal of Material Science, Japanese Journal of Applied Physics, etc. Holder of 30+ patents. Obtained SBIR Phases I, II contracts from NSF, Army, Navy, and US Ballistic Missiles. Awarded with research grants from Soros, NATO, CRDF, Fubright. |
Language Skills
| Language | Proficiency |
|---|---|
| Ukrainian | Fully Proficient |
| Russian | Fully Proficient |
Fields of Expertise
Czochralski process, Czochralski silicon crystal growth, silicon semiconductor growth, radiation hardness, semiconductor material, semiconductor material processing, semiconductor material property, semiconductor wafer, silicon wafer, semiconductor wafer processing, silicon wafer, semi-insulating substrate, nanomaterial, product defect, nanowire growth, nanopowder, nanocrystalline coating material, bulk silicon micromachining, microelectronic equipment, microelectronic chemical, nanoparticle, discrete semiconductor device, nanostructure, integrated-circuit manufacturing, neutron transmutation doping, four point probe, nonreactive ion etching, anisotropic etching, semiconductor dopant lateral diffusion, float zone single silicon crystal growth method, semiconductor electrode, heterojunction, heterojunction bipolar transistor, band gap, active region, semiconductor economics, microaccelerometer, rapid thermal semiconductor wafer processing, flatness, micromechanical system, semiconductor etching, epitaxial silicon, atmospheric pressure chemical vapor deposition, intrinsic semiconductor, energy band, rapid thermal processing, semiconductor defect analysis, chemical mechanical polishing, semiconductor integrated processing, electronics, semiconductor fabrication clean-room management, electronic product technology innovation, semiconductor material characterization, micro electrical-mechanical system, semiconductor material manufacturing, nanotechnology, advanced material, doping agent, semiconductor impurity material, nanocomposite, silicon-on-sapphire material, complementary metal-oxide semiconductor device, semiconductor device manufacturing, ion etching, micromechanics, microelectromechanics, acceptor impurity, metal-oxide semiconductor device, semiconductor chip, circuit integration, semiconductor ion implantation, semiconductor doping, semiconductor device, microsensor, microfabrication, microactuator, integrated circuit, semiconductor growth, epitaxy, semiconductor diffusion, chemical vapor deposition, bulk effect